In accordance with the prior art, a flash memory cell is programmed, erased and read with a common floating gate transistor.
FIG. 1A shows a memory cell arrangement 100 in AND logic combination as known from the prior art.
This arrangement has a multiplicity of memory cells 101 which are arranged in matrix form and are in each case arranged in a crossover region of a word line 102 and a bit line 103 running orthogonally with respect thereto. Each memory cell 101 has a floating gate transistor 104, the gate terminal 105 of which is coupled to one of the word lines 102. A first source/drain terminal 106 and a second source/drain terminal 107 of the transistor 104 are coupled to a bit line 103. Electrical charge carriers can be introduced and permanently stored in a floating gate layer 108, the stored information clearly being coded in the charge state of the floating gate layer.
A memory cell 101 is programmed by electrical charge carriers being introduced by means of Fowler-Nordheim tunneling into the floating gate layer 108 of the memory cell 102. In order to erase the memory content of a memory cell 101, a voltage of 5 volts is applied to both source/drain terminals 106, 107, whereas a voltage of −12 volts is applied to the gate terminal 105. In order to program information, the gate terminal 105 is brought to an electrical potential of 17 volts, whereas the two source/drain terminals 106, 107 are at an electrical potential of 0 volts. In order to read out the information stored in a memory cell 101, a voltage of 0 volts is applied to the first source/drain terminal 106, a voltage of 1 volt is applied to the second source/drain terminal 107 and a voltage of 2.5 volts is applied to the gate terminal 105. In accordance with the charge state of the floating gate layer 108, which characteristically influences the conductivity of the channel region of the floating gate transistor 104, an electrical signal is detected during read-out of a memory cell 101 on the associated bit line 103, the value of which signal is characteristic of the charge state of the floating gate layer 108.
FIG. 1B shows a schematic plan view of a part of the circuit arrangement 100.
Further, FIG. 1C schematically illustrates a memory cell arrangement 120 (NAND arrangement) as known from the prior art.
A common first source/drain terminal 121 and a common second source/drain terminal 122 are provided in the case of the memory cell arrangement 120. The memory cell arrangement 120 can be activated by means of two selection transistors 123. Information can be stored in each of the memory transistors 124 using a floating gate layer. The memory transistors 124 can be driven via gate lines 125.
FIG. 1D illustrates a schematic plan view of a memory cell arrangement 130 known from the prior art.
The memory cell arrangement 130 (NAND arrangement like FIG. 1C) has a bit line 131 with a bit line contact 132. A first selection line 133 and a second selection line 134 are furthermore shown. Moreover, a common source/drain terminal line 135 is shown. A multiplicity of memory cells 136 arranged parallel to one another are shown between selection lines 133 and 134. Each of the memory cells 136 has a floating gate region 137. Word lines 138 arranged in a manner running orthogonally with respect to the bit line 131 are furthermore shown.
FIG. 1E shows a circuit diagram view of the memory cell arrangement 130.
In particular, the selection transistors 139, 140 of the first selection line 133 and of the second selection line 134, respectively, are shown here. Floating gate transistors 141 of the memory cells 136 are furthermore shown.
To summarize, it should be emphasized that, in the case of the memory cell arrangements in accordance with the prior art as described with reference to FIG. 1A to FIG. 1E, the word line is arranged in a manner running orthogonally with respect to the bit line and for each memory cell a common transistor in each case is used for programming, erasing and reading.
However, in the case of memory cells of this type, there are problems with the transistors in the context of advancing miniaturization since the thickness of the gate insulating layer between floating gate and the channel region of a memory transistor cannot be reduced significantly below approximately 8 nm. The reason for this is that a sufficiently long retention time is necessary for storing the data stored in a floating gate transistor. The stored data are lost on account of electric creepage currents with a time constant that is often referred to as the retention time. The retention time is shorter the thinner a gate insulating layer is chosen to be.
In many cases it is not possible to miniaturize such a transistor whilst keeping the thickness of the gate insulating layer constant. In the case of such a transistor, the so-called “subthreshold slope”, that is to say clearly the dependence of the value of the drain current on a gate-source voltage below the threshold voltage, often becomes increasingly worse and the value of the electric current in the off state of the transistor becomes larger and larger.
Lin, X, Chan, M, Wang, H (2000) “Opposite Side Floating Gate SOI FLASH Memory Cell” Proceedings 2000 IEEE Hong Kong Electron Device Meeting, pages 12 to 15, illustrates the functioning of a flash memory cell with a read transistor provided separately from the memory transistor in a simulation study. In the case of the memory cell known from Lin et al., the electrical conductivity of the channel region is influenced by a floating gate on one side of said channel region and by a read gate on the other side of said channel region.
In order to produce such a memory cell, Lin et al. proposes patterning the silicon covering layer of an SOI substrate to form a read gate region, forming an electrically insulating layer thereon and epitaxially growing silicon material on said electrically insulating layer from the side using a laterally formed silicon seed region. However, with this growth method, a silicon layer with a sufficient quality cannot be achieved or can only be achieved with a very high outlay. On the layer sequence obtained in this way, a multiplicity of layers are deposited and patterned jointly, with the result that a flash memory cell with an extreme topology, i.e. surface structure is obtained which raises major problems in lithography particularly in a technology having feature sizes of less than 100 nm. Moreover, the production method presented in Lin et al. provides a tunnel layer made of silicon dioxide, which may possibly be destroyed under the action of the high programming voltages required for programming a memory cell of this type.
U.S. Pat. No. 6,252,275 B1 discloses a nonvolatile RAM memory cell based on a silicon-on-insulator technology.
U.S. Pat. No. 6,271,088 B1 discloses a method for the production of a buried memory cell with a vertically divided gate.
U.S. Pat. No. 5,306,935 discloses a method for forming a nonvolatile stacked memory.
U.S. Pat. No. 6,136,650 discloses a method for forming a three-dimensional flash memory structure.